1. Field of the Invention
This invention generally relates to an apparatus in which data pin usage is maximized and a method for maximizing data pin usage. In particular, this invention relates to a programmable logic device programmed to use a data pin bidirectionally.
2. Description of Related Art
In the field of electronics, considerations concerning miniaturization, chip count, and cost constantly drive designers to better utilize existing devices. A recent innovation has been the development of programmable logic devices, which allow a designer to condense a relatively large amount of loose logical circuitry into a single integrated device. These devices have given designers the opportunity to lower chip counts, and thus reduce board space and cost, by replacing groups of discrete logical devices with a single chip. Programmable logic devices, or PLDs, come in many varieties such as programmed array logic (PALs), programmed logic arrays (PLAs), and read only memories (ROMs).
But these devices only present an opportunity to reduce board space, component count, and cost. To best realize these savings, designers must use these devices as efficiently as possible. Currently, these devices' data pins are only programmed for use unidirectionally. An output signal is output to one pin, while an input signal is input from another. At best, such use requires an excessive number of pins on the PLD. At worst, such use leads to the need for more devices than would otherwise be necessary.
As an illustration of this unidirectional use of PLD data pins, FIGS. 1 and 2 show how PLDs would generally be configured when a circuit requires data to be both received on and driven to a particular line. FIG. 1 illustrates, for example, how two PLDs of the prior art would be used. One PLD would input the data, as illustrated by PAL1, using the VALID(3:0) lines as inputs; another PLD would selectably drive the data lines, as illustrated by PAL2 selectably driving the VALID(3:0) lines through the use of PAL2 output enable line OE.
The circuit of FIG. 2 illustrates the wastefulness of this approach. In that circuit, PAL1 receives as inputs the VALID(3:0) lines, while PAL2 uses its data pins as outputs to drive the VALID(3:0) lines. Thus, two devices, or at least two pins, are required to input from and output to each VALID(3:0) line.
If a way to further maximize the usage of the data pins could be developed, it would have the potential of reducing chip count and the number of required pins, thus reducing cost and board space. Therefore, it would be desirable to maximize programmable data pin usage on PLDs to reduce chip count and the required number of pins, thus further reducing board size and cost.